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CS5529
16-Bit, Programmable ADC with 6-Bit Latch
Features
l Delta-Sigma
General Description
Analog-to-Digital Converter
The 16-bit CS5529 is a low-power programmable Analog-to-Digital Converter (ADC) which includes coarse/fine charge buffers, a fourth order modulator, a calibration microcontroller, a digital filter with programmable decimation rates, a 6-bit output latch, and a threewire serial interface. The ADC is designed to operate from single or dual analog supplies and a single digital supply. The digital filter is programmable with output update rates between 1.88 Hz to 101 Hz. These output rates are specified for XIN = 32.768 kHz. Output word rates can be increased by approximately 3X by using XIN = 100 kHz. The filter is designed to settle to full accuracy for the selected output word rate in one conversion. When operated at word rates of 15 Hz or less, the filter rejects both 50 Hz and 60 Hz simultaneously. Low power, single conversion settling time, programma-
- Linearity Error: 0.0015%FS - Noise Free Resolution: 16-Bits
l 2.5
V Bipolar/Unipolar Buffered Input Range l 6-Bit Output Latch l Eight Digital Filters
- Selectable Output Word Rates - Output Settles in One Conversion Cycle - 50/60 Hz 3 Hz Simultaneous Rejection
l Simple
three-wire serial interface
- SPITM and MicrowireTM Compatible - Schmitt Trigger on Serial Clock (SCLK)
l System/Self-Calibration
with R/W Registers l Power Supply Configurations
- VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V ble output rates, and the ability to handle negative input - VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V signals make this single or dual supply product an ideal
l Low
Power Consumption: 2.5 mW
solution for isolated and non-isolated applications. ORDERING INFORMATION See page 27.
VA+ AIN+ 1X AINVREF+ 1X VREF-
VA-
DGND
VD+
Differential 4th Order Delta-Sigma Modulator
Digital Filter
Calibration Register
CS SCLK
Control Register
SDI
Latch
Calibration Memory
Calibration C
Clock Gen.
Output Register
SDO
A0 A1 D0 D1 D2 D3
XIN
XOUT
Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com
Copyright (c) Cirrus Logic, Inc. 1999 (All Rights Reserved)
MAR `99 DS246F1 1
CS5529
TABLE OF CONTENTS
TABLE OF CONTENTS ....................................................................................... 2 TABLE OF FIGURES .......................................................................................... 3 CHARACTERISTICS/SPECIFICATIONS ............................................................ 4 ANALOG CHARACTERISTICS................................................................... 4 5 V DIGITAL CHARACTERISTICS ............................................................. 6 3 V DIGITAL CHARACTERISTICS ............................................................. 6 DYNAMIC CHARACTERISTICS ................................................................. 6 ABSOLUTE MAXIMUM RATINGS .............................................................. 7 SWITCHING CHARACTERISTICS ............................................................. 8 GENERAL DESCRIPTION ................................................................................ 10 Analog Input ............................................................................................. 10 Analog Input Model ............................................................................ 10 Voltage Reference Input Model .......................................................... 10 Serial Port ................................................................................................. 11 Command Register Descriptions ........................................................ 12 Serial Port Interface ........................................................................... 13 Serial Port Initialization ....................................................................... 15 System Initialization ........................................................................... 15 Configuration Register .............................................................................. 15 Latch Output Pins ............................................................................... 15 Power Consumption ........................................................................... 15 Output Word Rate .............................................................................. 16 Digital Filter ........................................................................................ 16 Clock Generator ................................................................................. 16 Reset System ..................................................................................... 16 Port Flag ............................................................................................. 17 Calibration .......................................................................................... 17 Calibration Registers ................................................................... 17 Offset Register ...................................................................... 17 Gain Register ........................................................................ 18 Self Calibration ............................................................................ 18 System Calibration ....................................................................... 18 Limitations in Calibration Range .................................................. 19 Calibration Tips ............................................................................ 19 Configuration Register Descriptions ................................................. 20 Performing Conversions ........................................................................... 21 Performing Conversions with PF bit = 0 ............................................. 21 Performing Conversions with PF bit = 1 ............................................. 21 Single Conversion ........................................................................ 21 Continuous Conversions .............................................................. 21 Output Coding .................................................................................... 22 Power Supply Arrangements .................................................................... 23 PCB Layout .............................................................................................. 24 PIN DESCRIPTIONS ......................................................................................... 25 Clock Generator......................................................................................... 25 Control Pins and Serial Data I/O................................................................ 25 Measurement and Reference Inputs ......................................................... 26 Power Supply Connections........................................................................ 26 SPECIFICATION DEFINITIONS ........................................................................ 27 ORDERING GUIDE ............................................................................................ 27 PACKAGE DIMENSIONS ................................................................................. 28
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TABLE OF FIGURES
Input models for AIN+ and AIN- pins......................................................... 11 Input model for VREF+ and VREF- pins. .................................................. 11 CS5529 Register Diagram. ....................................................................... 11 Command and Data Word Timing. ............................................................ 14 Filter Response (Normalized to Output Word Rate = 1)............................ 16 Self Calibration of Offset. .......................................................................... 18 Self Calibration of Gain. ............................................................................ 18 System Calibration of Offset...................................................................... 18 System Calibration of Gain........................................................................ 19 CS5529 Configured with a +5.0 V Analog Supply..................................... 23 CS5529 Configured with 2.5 V Analog Supplies. .................................... 23
SPITM is a trademark of Motorola Inc., MicrowireTM is a trademark of National Semiconductor Corp. Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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CHARACTERISTICS/SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = 25 C; VA = 2.5 V 5%, VD+ = 5 V 5%, VREF+ = 2.5 V, VREF- = 0.0 V, FCLK = 32.768 kHz, OWR (Output Word Rate) = 15 Hz, Bipolar Mode, Input Range = 2.5 V.) (See Notes 1 and 2.)
Parameter Min 16 (Note 3) (Note 3) (Notes 3 and 4) (Note 4) Typ 0.0015 1 2 11 8 16 1 Max 0.003 2 4 31 63 Unit %FS Bits LSB16 LSB16 nV/C ppm ppm ppm/C
Accuracy Linearity Error No Missing Codes Bipolar Offset
Unipolar Offset Offset Drift Bipolar Gain Error Unipolar Gain Error Gain Drift
Noise (Notes 5 and 6)
Output Word Rate (Hz) 1.88 3.76 7.51 15.0 30.0 61.6 84.5 101.1 -3 dB Filter Frequency (Hz) 1.64 3.27 6.55 12.7 25.4 50.4 70.7 84.6 Noise (V) 4.5 5.0 7.0 15 45 190 900 3000
Notes: 1. Applies after system calibration at any temperature within -40 C ~ +85 C. 2. Specifications guaranteed by design, characterization, and/or test. 3. Specification applies to the device only and does not include any effects by external parasitic thermocouples. 4. Drift over specified temperature range after calibration at power-up at 25 C. 5. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 C. 6. For peak-to-peak noise multiply by 6.6 for all ranges and output rates. Specifications are subject to change without notice.
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ANALOG CHARACTERISTICS (Continued)
Parameter Analog Input Common Mode + Signal on AIN+ or AIN(Bipolar/Unipolar Mode) Single Supply Dual Supply Common Mode Rejection dc 50, 60Hz Input Capacitance CVF Current AIN+, AIN(Note 7) System Calibration Specifications Full Scale Calibration Range, with VREF = 2.5 V (Note 8) Offset Calibration Range (Bipolar/Unipolar Mode) Voltage Reference Input Range {(VREF+) - (VREF-)} (Note 9) REF+ REFCommon Mode Rejection dc 50, 60 Hz Input Capacitance CVF Current (Note 7) Power Supplies DC Power Supply Currents (Normal Mode) IA+ ID+ Power Consumption Normal Mode Low Power Mode Standby Sleep dc Positive Supplies dc Negative Supply (Note 10) Min Typ Max Unit
0.0 VA1.0 1.0 VAVA-
120 120 10 16 2.5 110 130 16 8
VA+ VA+ 3.5 1.25 5 VA+ VA+ -
V V dB dB pF nA V V V V V dB dB pF nA
-
360 95 2.5 1.4 1 500 80 80
450 150 2.875 2.2 -
A A mW mW mW W dB dB
Power Supply Rejection
Notes: 7. See the section of the data sheet which discusses Analog Input Models. 8. The minimum Full Scale Calibration Range (FSCR) is limited by the maximum allowed gain register value (with margin). The maximum FSCR is limited by the modulator's 1's density range. See "Analog Input" section for details. Also see "Limitations in Calibration Range". 9. VREF must be less than or equal to supply voltages. 10. All outputs unloaded. All inputs CMOS levels.
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5 V DIGITAL CHARACTERISTICS (TA = 25 C; VA = 2.5V
and 11.) Parameter High-Level Input Voltage: All Pins Except XIN, SCLK XIN SCLK XIN, SCLK XIN SCLK SDO (Note 12) SDO, Iout = -5.0mA SDO, Iout = 1.6mA SDO, Iout = 5.0mA Symbol VIH VIH VIH VIL VIL VIL VOH VOH VOL VOL Iin IOZ Cout Min 0.6VD+ (VD+)-0.9 (VD+)-0.45 (VD+)-1.0 (VD+)-1.0 Typ 1 9 Max 0.8 2.0 0.6 0.4 0.4 10 10 Unit V V V V V V V V V V A A pF 5%, VD+ = 5V 5%.)(See Notes 2
Low-Level Input Voltage:
All Pins Except
High-Level Output Voltage: Low-Level Output Voltage: Input Leakage Current 3-State Leakage Current
All Pins Except All Pins Except
Digital Output Pin Capacitance Notes: 11. All measurements performed under static conditions.
12. Iout = -100 A unless stated otherwise. (VOH = 2.4 V @ Iout = -40 A).
3 V DIGITAL CHARACTERISTICS (TA = 25 C; VA = 2.5 V 5%, VD+ = 3.0 V 5%.)
(See Notes 2 and 11.) Parameter High-Level Input Voltage: All Pins Except XIN, SCLK XIN SCLK XIN, SCLK XIN SCLK SDO, Iout = -400 A SDO, Iout = -5.0 mA SDO, Iout = 400 A SDO, Iout = 5.0 mA Symbol VIH VIH VIH VIL VIL VIL VOH VOH VOL VOL Iin IOZ Cout Min 0.6VD+ (VD+)-0.9 (VD+)-0.45 (VD+)-0.3 (VD+)-1.0 Typ 1 9 Max 0.16 VD+ 0.5 0.6 0.3 0.4 10 10 Unit V V V V V V V V V V A A pF
Low-Level Input Voltage:
All Pins Except
High-Level Output Voltage: Low-Level Output Voltage: Input Leakage Current 3-State Leakage Current
All Pins Except All Pins Except
Digital Output Pin Capacitance
DYNAMIC CHARACTERISTICS
Parameter Modulator Sampling Frequency Filter Settling Time to 1/2 LSB (Full Scale Step) Symbol fs ts Ratio XIN/4 1/fout Units Hz s
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ABSOLUTE MAXIMUM RATINGS (DGND = 0 V) (See Note 13.)
Parameter DC Power Supplies (Notes 14 and 15) Positive Digital Positive Analog Negative Analog (Notes 16 and 17) (Note 18) AIN and VREF pins Symbol VD+ VA+ VAIIN IOUT PDN VINA VIND TA Tstg Min -0.3 -0.3 -6.0 (VA-) + (-0.3) -0.3 -40 -65 Typ Max +6.0 +6.0 +0.3 10 25 8 (VA+)+0.3 (VD+)+0.3 +85 +150 Unit V V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 13. All voltages with respect to ground. 14. VA+ and VA- must satisfy {(VA+) - (VA-)} +6.0 V. 15. VD+ and VA- must satisfy {(VD+) - (VA-)} +7.75 V. 16. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 17. Transient current of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 18. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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SWITCHING CHARACTERISTICS (TA = 25 C; VA = 2.5 V 5%, VD+ = 3 V 5% or 5 V 5%;
Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50pF) Parameter Master Clock Frequency: Master Clock Duty Cycle Rise Times (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output XTAL = 32.768 kHz (Note 21) trise trise tost tpor 50 500 1002 1.0 100 s s ns ms XIN cycles MHz ns ns ns ns ns ns ns ns ns 50 1.0 100 s s ns External Clock or Internal Oscillator (Note19) Symbol XIN Min 30 40 Typ 32.768 Max 100 60 Unit kHz %
Fall Times
Start-up Oscillator Start-up Time
Power-on Reset Period
Serial Port Timing Serial Clock Frequency Serial Clock SDI Write Timing CS Enable to Valid Latch Clock
Data Set-up Time prior to SCLK rising Data Hold Time After SCLK Rising SCLK Falling Prior to CS Disable
SCLK Pulse Width High Pulse Width Low t1 t2 t3 t4 t5 t6 t7 t8 t9
0 250 250 50 50 100 100 -
-
2 150 150 150
SDO Read Timing CS to Data Valid
SCLK Falling to New Data Bit CS Rising to SDO Hi-Z
Notes: 19. Device parameters are specified with 32.768 kHz clock, however, clocks up to 100 kHz can be used for increased throughput. 20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source.
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CS
t3
t1
t6
SCLK
t2
Continuous Running SCLK Timing (Not to Scale)
CS
t3
SDI
MSB
MSB-1
t4 t5 t1
LSB
t6
SCLK
t2
SDI Write Timing (Not to Scale)
CS
t7 t9
SDO
MSB
t8
MSB-1
t2
LSB
SCLK
t1
SDO Read Timing (Not to Scale)
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CS5529
GENERAL DESCRIPTION
The CS5529 is a 16-bit Analog-to-Digital Converter (ADC) which includes coarse/fine charge buffers, a fourth order modulator, a calibration microcontroller, eight digital filters which provide selectable decimation rates, a 6-bit output latch, and a three-wire serial interface. The ADC is optimized to digitize unipolar or bipolar signals in industrial applications. The digital filters provide eight selectable output word rates (OWRs) of 1.88 Hz, 3.76 Hz, 7.51 Hz, 15.0 Hz, 30.0 Hz, 61.6 Hz, 84.5 Hz, 101.1 Hz when operated from a 32.768 kHz watch crystal or equivalent clock (output word rates can be increased by approximately 3X by using 100 kHz clock). The filters are designed to settle to full accuracy for the selected output word rate in one conversion. When operated at word rates of 15 Hz or less (XIN = 32.768 kHz), the filter rejects both 50 Hz and 60 Hz line interference simultaneously. Note that to keep from saturating the analog front end, the input span must stay at or below 1.5 times the reference voltage. This corresponds to a gain register of 0.666... when a 2.5 V reference voltage is used.
Note: When a smaller reference voltage is used, the resulting code widths are smaller. Since the output codes exhibit more changing codes for a fixed amount of noise, the converter appears noisier.
Calibration can also affect the ADC's full scale span because system gain calibration can be used to increase or decrease the full scale span of the ADC's transfer functions. At its limit, the input full scale can be reduced to the point in which the gain register reaches its upper limit of 3.999... (this will occur when the ADC is gain calibrated with an input signal less than or equal to approximately 1/4 of its nominal full scale, if the ADC does not have intrinsic gain error). Calibration and its effects on the analog input span is detailed in a later section of the data sheet.
Analog Input
The CS5529 provides a nominal 2.5 V input span when the gain register is 1.0 decimal and the differential reference voltage between VREF+ and VREF- is 2.5 V. The gain registers content is used during calibration to set the gain slope of the ADC's transfer function. The differential reference voltage magnitude and the gain register are two factors that can be used to scale the nominal 2.5 V input span. After reset, the gain register defaults to 1.0 decimal. In this case, the external voltage between the VREF+ pin and the VREF- pin sets the ADC's nominal full scale input span to 2.5 V. If a user want to modify the input span, either the gain register or the reference voltage's magnitude needs to be changed. For example, if a 1.25 V reference is used in place of the nominal 2.5 V input, the fullscale span is cut in half. To achieve the same 1.25V input span, the user could simply use a 2.5 V reference and modify the gain register to 2.0 decimal.
Analog Input Model
Figure 1 illustrates the input models for the AIN pins. The model includes a coarse/fine charge buffer which reduces the dynamic current demands from the signal source. The buffer is designed to accommodate rail to rail (common-mode plus signal) input voltages. Typical CVF (sampling) current is about 16nA (XIN = 32.768 kHz, see Figure 1). Application Note 30, "Switched-Capacitor A/D Input Structures", details various input architectures.
Voltage Reference Input Model
Figure 2 illustrates the input models for the VREF pins. It includes a coarse/fine charge buffer which reduces the dynamic current demand of the external reference. Typical CVF (sampling) current is about 8nA (XIN = 32.768 kHz, see Figure 2). The reference's buffer is designed to accommodate rail-to-rail (common-mode plus signal) input voltDS246F1
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1Fine 1Coarse C = 20pF 1Fine 2Coarse C = 10pF f = 32.768 kHz
Figure 2. Input model for VREF+ and VREF- pins.
AIN Vos 25mV i n = fVos C
VREF Vos 25mV i n = fVos C
f = 32.768 kHz
Figure 1. Input models for AIN+ and AIN- pins.
ages. The differential voltage between VREF+ and VREF- sets the nominal full scale input span of the converter. For a single-ended reference voltage, such as the LT1019-2.5, the reference output is connected to the VREF+ pin of the CS5529 and the ground reference for the LT1019-2.5 is connected to the VREF- pin.
ure 3 illustrates a block diagram of all the internal register. After a system initialization or reset, the serial port is set to the command mode. The converter stays in this mode until a valid 8-bit command is received (the first 8-bits into the serial port). Once a valid 8bit command is received and interpreted by the ADC's command register, the serial port enters the data mode. In data mode the next 24 serial clock pulses shift data either into or out of the serial port (72 serial clock pulses are needed if the setup register command is issued). The Command Register Descriptions section illustrates all valid commands.
Serial Port
The CS5529 includes a microcontroller with a command register, a configuration register, a conversion data register (read only), and a gain and offset register for calibration. All registers, except the 8-bit command register, are 24-bits in length. Fig-
Offset Register (1 x 24)
Gain Register (1 x 24)
Read Only
Conversion Data Register (1x24)
CS
Serial Interface Write Only
SDI
SDO SCLK
Configuration Register (1 x 24)
Latch Outputs Low Power Mode Output Word Rates Unipolar/Bipolar Reset System etc.
Command Register (1 x 8)
Figure 3. CS5529 Register Diagram.
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Command Register Descriptions
D7(MSB) CB BIT D7 D6 SC D5 CC NAME Command Bit, CB D4 R/W D3 RSB2 VALUE 0 1 D6 D5 D4 D3-D1 Single Conversion, SC Continuous Conversions, CC Read/Write, R/W Register Select Bit, RSB2RSB0 0 1 0 1 0 1 000 001 010 011 100 101 110 111 0 1 D2 RSB1 D1 RSB0 D0 PS/R FUNCTION Null command (no operation). All command bits, including CB must be 0. Logic 1 for executable commands. Single Conversion not active. Perform a conversion. Continuous Conversions not active. Perform conversions continuously. Write to selected register. Read from selected register. Offset Register Gain Register Configuration Register Conversion Data Register (read only) Set-up Registers (Offset, Gain, Configuration) Reserved Reserved Reserved Run Power Save
D0
Power Save/Run, PS/R
Table 1. Command Set
Perform Single Conversion
7 1 6 1 5 0 4 0 3 0 2 0 1 0 0 0
This command instructs the ADC to perform a single conversion.
Perform Continuous Conversions
7 1 6 0 5 1 4 0 3 0 2 0 1 0 0 0
This command instructs the ADC to perform continuous conversions.
Power Save/Run
7 1 6 0 5 0 4 0 3 0 2 0 1 0 0 PS/R
If PS/R = 0, normal run mode is entered. If PS/R = 1, power save mode is entered.
Null
7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0
This command is used to clear the port flag in the continuous conversion mode when the port flag bit in the configuration register is set to logic 1.
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SYNC1
7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1
Part of the serial port re-initialization sequence (see text for use of command).
SYNC0
7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 0
End of the serial port re-initialization sequence.
Read/Write Registers
7 1 6 0 5 0 4 R/W 3 RSB2 2 RSB1 1 RSB0 0 0
These commands are used to perform a write to or a read from a specific register. The register to be accessed is selected with the RSB2-RSB0 bits of the command word. R/W 0 1 RSB[4:0] Write Register Read Register
Register address binary encoded 0 to 31 as follows. All registers are 24 bits long. Description Address 000 Read or Write Offset Register 001 Read or Write Gain Register 010 Read or Write Configuration Register 011 Read Conversion Data Register 100 Read or Write Offset Gain and Configuration Registers in this sequence (i.e. one 8-bit command is followed by 72-bits of data to access the Offset, then the Gain, and then the Configuration register)
Serial Port Interface
The CS5529's serial interface consists of four control lines: CS, SDI, SDO, and SCLK. CS, Chip Select, is the control line which enables access to the serial port. If the CS pin is tied to logic 0, the port can function as a three wire interface. SDI, Serial Data In, is the data signal used to transfer data to the converters. SDO, Serial Data Out, is the data signal used to transfer output data from the converters. The SDO output will be held at high impedance any time CS is at logic 1. SCLK, Serial Clock, is the serial bit-clock which controls the shifting of data to or from the ADC's serial port. The CS pin must be held at logic 0 before SCLK transitions can be recognized by the
port logic. To accommodate opto-isolators SCLK is designed with a Schmitt-trigger input to allow an opto-isolator with slower rise and fall times to directly drive the pin. Additionally, SDO is capable of sinking or sourcing up to 5 mA to directly drive an opto-isolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA. Figure 4 illustrates the serial sequence necessary to write to, or read from the serial port's registers. A transfer of data is always initiated by sending the appropriate 8-bit command (MSB first) to the serial port (SDI pin). It is important to note that some commands use information from the configuration registers to perform the function. For those commands it is important that the correct information is written to the configuration register first.
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CS
SCLK
SDI Command Time 8 SCLKs
MSB
LSB
Data Time 24 SCLKs (or 72 SCLKs for Set-up Registers) Write Cycle
CS
SCLK
SDI Command Time 8 SCLKs SDO
MSB LSB
Data Time 24 SCLKs (or 72 SCLKs for Set-up Registers)
Read Cycle
SCLK
SDI
Command Time 8 SCLKs SDO * td = XIN/OWR clock cycles for each conversion except the first conversion which will take XIN/OWR + 7 clock cycles SDO Continuous Conversion Read (PF bit = 1) td * XIN/OWR Clock Cycles
8 SCLKs Clear SDO Flag
MSB
LSB
Data Time 24 SCLKs
Figure 4. Command and Data Word Timing.
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Serial Port Initialization
The serial port is initialized to the command mode whenever a power-on reset is performed or when the port initialization sequence is completed. The port initialization sequence involves clocking fifteen (or more) SYNC1 command bytes (0xFF) followed by one SYNC0 command byte (0xFE). This sequence places the chip in the command mode where it waits until a valid command is received. This function does not reset the internal registers to their default settings. It only resets the serial port to the command mode.
Latch Output Pins
The D3-D0 pins of the converter mimic the D21D18 bits of the configuration register. D3-D0 can be used to control multiplexers and other digital logic functions outside the converter. The D0-D3 outputs are powered from VD+ and DGND. Their output voltage will be VD+ for a logic 1 and DGND for a logic 0. The A1-A0 pins of the converter mimic the D23-D22 bits of the configuration register and can be used to control analog switches. These outputs are powered from VA+ and VA-, hence, their output voltage will be either VA+ for a logic 1 or VA- for a logic 0. All outputs can sink or source at least 1 mA, but it is recommended to limit drive currents to less than 20 A to reduce self-heating of the chip.
System Initialization
When power to the CS5529 is applied, the chip is held in a reset condition until the 32.768 kHz oscillator has started and a counter-timer elapses. Due to the high Q of the 32.768 kHz crystal, the oscillator takes 400-600 ms to start. The counter-timer counts 1002 oscillator clock cycles to make sure the oscillator is fully stable. During this time-out period the serial port logic is reset and the RV (Reset Valid) bit in the configuration register is set to indicate that a valid reset occurred. After a reset, the on-chip registers are initialized to the following states and the converter is placed in the command mode where it waits for a valid command.
Configuration Register: Offset Register: Gain Register: Note: 000040(H) 000000(H) 400000(H)
Power Consumption
The CS5529 accommodates four power consumption modes: normal, low power, standby, and sleep. The normal mode, the default mode, is entered after a power-on-reset and typically consumes 2.5 mW. The low power mode is an alternate mode that reduces the consumed power to 1.4 mW. It is entered by setting bit D16 (the low power mode bit) in the configuration register to logic 1. Since the converter's noise and linearity performance improves with increased power consumption, slightly degraded noise or linearity performance should be expected in the low power mode. The final two modes are the power save modes. These modes power down most of the analog portion of the chip and stop filter convolutions. The power save modes are entered whenever the Power Save (0x81 hexadecimal) command is issued to the serial port. The particular power save mode entered depends on state of bit D4 (the power save select bit) in the configuration register. If D4 is logic 0, the converter enters the standby mode reducing the power consumption to 1 mW. The standby mode leaves the oscillator and the on-chip bias generator
A system reset can be initiated at any time by writing a logic 1 to the RS (Reset System) bit in the configuration register. After a reset, the RV (Reset Valid) bit is set until the configuration register is read. The user must then write a logic 0 to the RS bit to take the part out of the reset mode.
Configuration Register
The configuration register is a 24 bit register used to modify the functions of the ADC. The following sections detail the functions of the bits in the configuration register.
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running. This allows the converter to quickly return to the normal or low power mode once the PS/R bit is set back to a logic 0. If D4 in the configuration register is logic 1 and Power Save command is issued, the sleep mode is entered reducing the consumed power to less than 10 W. Since the sleep mode disables the oscillator, approximately a 500 ms crystal oscillator start-up delay period is required before returning to the normal or low power mode. If an external clock is used, the chip should start within a few microseconds. better than 80 dB rejection for both 50 Hz and 60 Hz with output word rates at or below 15.0 Hz (XIN = 32.768 kHz). The converter's digital filters scale with XIN. For example with an output word rate of 15 Hz, the filter's corner frequency is typically 12.7 Hz. If XIN is increased to 64.536 kHz the OWR doubles and the filter's corner frequency moves to 25.4 Hz.
Clock Generator
The CS5529 includes a gate which can be connected with an external crystal to provide the master clock for the chip. The chip is designed to operate using a low-cost 32.768 kHz "tuning fork" type crystal. One lead of the crystal should be connected to XIN and the other to XOUT. Lead lengths should be minimized to reduce stray capacitance. Note that the converter will operate with an external (CMOS compatible) clock with frequencies up to 100 kHz.
Output Word Rate
The WR2-WR0 bits of the configuration register set the output conversion word rate of the converter as shown in the Configuration Register Descriptions table. The word rates indicated in the table assume a master clock of 32.768 kHz. Upon reset the converter is set to operate with an output word rate of 15.0 Hz.
Digital Filter
The CS5529 has eight different linear phase digital filters which set the output word rates (OWRs) as stated in Configuration Register Descriptions. These rates assume that XIN is 32.768 kHz. Each of the filters has a magnitude response similar to that shown in Figure 5. The filters are optimized to settle to full accuracy every conversion and yield
Reset System
The reset system bit permits the user to perform a hardware reset. A hardware reset can be initiated at any time by writing a logic 1 to the RS (Reset System) bit in the configuration register. After a hardware reset cycle is complete, the serial port logic is reset and the RV (Reset Valid) bit in the configuration register is set to indicate that a valid reset occurred. After a reset, the on-chip registers are initialized to the following states and the converter is placed in the command mode where it waits for a valid command.
Configuration Register: Offset Register: Gain Register: Note: 000040(H) 000000(H) 400000(H)
Figure 5. Filter Response (Normalized to Output Word Rate = 1).
A system reset can be initiated at any time by writing a logic 1 to the RS (Reset System) bit in the configuration register. After a reset, the RV (Reset Valid) bit is set until the configuration register is read. The user must then write a logic 0 to the RS bit to take the part out of the reset mode.
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CS5529
Port Flag
The port flag bit in the configuration register allows the user to select the mode in which conversions will be presented to the serial port. With the port flag bit cleared, the user must read the conversion data register. With the port flag bit set to logic 1, the user can read the conversion data from the serial port by first issuing the NULL command to clear the SDO flag and then issuing 24 SCLKs to read the conversion word. version cycles to complete and will set the DF bit after the gain calibration is completed.
Note: 1) The DF bit will be cleared any time the data register, the offset register, the gain register, or the setup register is read. Reading the configuration register alone will not clear the DF bit. 2) After the CS5529 is reset, the converter is functional and can perform measurements without being calibrated. In this case, the converter will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate output words. Any initial offset and gain errors in the internal circuitry of the chip will remain.
Calibration
Calibration is used to set the zero and gain slope of the ADC's transfer function. The calibration control bits in the configuration register allow the user to perform either self calibration or system calibration. The offset and gain calibration steps each take one conversion cycle to complete. At the end of the calibration step, the calibration control bits will be set back to logic 0, and the DF (Done Flag) bit will be set to a logic 1. For the combination self-calibration (CC2-CC0= 011; offset calibration followed by gain calibration), the calibration will take two conOffset Register
23(MSB) Sign 0 11 2-13 0 22 2-2 0 10 2-14 0 21 2-3 0 9 2-15 0 20 2-4 0 8 2-16 0 19 2-5 0 7 2-17 0 18 2-6 0 6 2-18 0 17 2-7 0 5 2-19 0
Calibration Registers
The offset calibration result is stored in the offset register. The result is used during the conversion process to nullify offset errors. One LSB in the offset register is 2-24 proportion of the input span (bipolar span is 2 times the unipolar span). The MSB in the offset register determines if the offset to be trimmed is positive or negative (0 positive, 1 negative). The converter can typically trim 50 percent of the input span. Refer to the following Offset Register and Gain Register descriptions for details.
16 2-8 0 4 2-20 0
15 2-9 0 3 2-21 0
14 2-10 0 2 2-22 0
13 2-11 0 1 2-23 0
12 2-12 0 0 2-24 0
One LSB represents 2-24 proportion of the input span (bipolar span is 2 times unipolar span). Offset and data word bits align by MSB (bit MSB-4 of offset register changes bit MSB-4 of data). After reset, all bits are `0'.
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CS5529
Gain Register
23(MSB) 21 0 11 2-11 0 22 20 0 10 2-12 0 21 2-1 0 9 2-13 0 20 2-2 0 8 2-14 0 19 2-3 0 7 2-15 0 18 2-4 0 6 2-16 0 17 2-5 0 5 2-17 0 16 2-6 0 4 2-18 0 15 2-7 0 3 2-19 0 14 2-8 0 2 2-20 0 13 2-9 0 1 2-21 0 12 2-10 0 0 2-22 0
The gain register span is from 0 to (4-2-22). After Reset the (MSB-1) bit is `1', all other bits are `0'.
The gain calibration results is stored in the gain register. The result sets the slope of the ADC's transfer function. The gain register spans from 0 to (4 - 2-22). The decimal equivalent meaning of the gain register is
N 1 0 -1 -N 1 D = b MSB 2 + ( b 0 2 + b 1 2 + ... + b N 2 ) = b MSB 2 +
OPEN AIN+ +
AINVREF+ Reference + - VREF-
OPEN
-
bi2
i=0
-i
CLOSED CLOSED
where the binary numbers have a value of either zero or one (b0 corresponds to bit MSB-1, N = 22).
Figure 7. Self Calibration of Gain.
Self Calibration
The CS5529 offers both self offset and self gain calibrations. For the self-calibration of offset, the converter internally ties the inputs of the modulator together and routes them to the VREF- pin as shown in Figure 6. Also self offset calibration requires that VREF- be tied to a fixed voltage between VA+ and VA-. For self-calibration of gain, the differential inputs of the modulator are connected to VREF+ and VREF- as shown in Figure7.
System Calibration
For the system calibration functions, the user must input signals which represent system ground and system full scale to the converter. When a system offset calibration is performed a ground reference signal must be applied to the converter (see Figure 8). When a system gain calibration is performed, the user must input a signal representing the positive full scale point as shown in Figure 9. In either case, calibration signals must be within the specified calibration limits for each specific calibration step (refer to the System Calibration Specifica-
S1 OPEN S3 CLOSED AIN+ +
External Connections + AIN+ 0V + -
AINVREF-
S2 OPEN S4 CLOSED
AIN-
Figure 6. Self Calibration of Offset.
Figure 8. System Calibration of Offset.
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Calibration Tips
External Connections + AIN+ Full Scale + AIN-
Figure 9. System Calibration of Gain.
Calibration steps are performed at the output word rate selected by the WR2-WR0 bits of the configuration register. Since higher word rates result in conversion words with more peak-to-peak noise, calibration should be performed at lower output word rates. Also, to minimize digital noise near the device, the user should wait for each calibration step to be completed before reading or writing to the serial port. Factory calibration can be performed in a user's system by using the system calibration capabilities of the CS5529. After the ADC is calibrated in the user's system, the offset and gain register contents can be read by the system microcontroller and recorded in EEPROM. These same calibration words can then be uploaded into the offset and gain registers of the converter when power is first applied to the system. A user can scale the input range by modifying the gain register. For example, if a self or system calibration is performed with a full scale of 2.5 V and a full scale of 1.25 V is desired, the user can modify the gain register to double its slope. This can be done by reading the gain register, shifting the binary word one position to the left (this multiplies the gain word by 2), and writing this word back into the gain register. The gain register can be scaled by any amount as long as it does not exceed a decimal range of 0.25 to 4.0. One of two methods can be used to determine when a calibration is complete: 1) if the PF (Port Flag) bit of the configuration register is set to logic 1, SDO falls to logic 0 at the completion of a calibration; or 2) regardless of the PF bit, the DF (Done Flag) bit in the configuration register is set at completion of calibration. The user can either monitor the DF bit or SDO to determine when a calibration is complete. Whichever method is used, the calibration control bits (CC2-CC0) automatically return to logic 0 upon completion of any calibration.
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tions). If a system gain calibration is performed, the calibrated input must not cause the resulting gain register's content, decoded in decimal, to exceed 3.9999998. The above condition requires that the full scale input voltage to be greater than 25 percent of the differential reference voltage (i.e. a 625mV input signal must be applied if the differential reference voltage is 2.5V).
Limitations in Calibration Range
System calibration can be limited by signal headroom in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. For gain calibration the full scale input signal can be reduced to the point in which the gain register reaches its upper limit of (4-2-22 decimal) or FFFFFF (hexadecimal). Under nominal conditions, this occurs with a full scale input signal equal to about 1/4 the reference voltage. With the converter's intrinsic gain error, this full scale input signal may be higher or lower. In defining the minimum Full Scale Calibration Range (FSCR) under "Analog Characteristics", margin is retained to accommodate the intrinsic gain error. Alternatively the input full scale signal can be increased to a point which exceeds the operating range of the analog circuitry. This occurs when the input voltage is approximately 1.5X the differential reference voltage (Gain Register = 1.0).
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Configuration Register Descriptions
D23(MSB) A1 D11 NU D22 A0 D10 NU D21 D3 D9 NU D20 D2 D8 NU D19 D1 D7 RS D18 D0 D6 RV D17 NU D5 PF D16 LPM D4 PSS D15 WR2 D3 DF D14 WR1 D2 CC2 D13 WR0 D1 CC1 D12 U/B D0 CC0
BIT
NAME
VALUE 00 0000 0 0 1 000 001 010 011 100 101 110 111 0 1 0 0 1 0 1 0 1 0 1 0 1 000 001 010 011 100 101 110 111
FUNCTION R* Latch Output Pins A1-A0 mimic the D23-D22 Register bits. R* Latch Output Pins D3-D0 mimic the D21-D18 Register bits. R Must always be logic zero. R Normal Mode ( 2.5 mW) Reduced Power Mode ( 1 mW) R 15.0 Hz (2180 XIN cycles) 30.0 Hz (1092 XIN cycles) 61.6 Hz (532 XIN cycles) 84.5 Hz (388 XIN cycles) 101.1 Hz (324 XIN cycles) 1.88 Hz (17444 XIN cycles) 3.76 Hz (8724 XIN cycles) 7.51 Hz (4364 XIN cycles) R Bipolar Measurement mode Unipolar Measurement mode R Must always be logic 0. R Normal Operation Activate a Reset cycle. To return to normal operation this bit must be written back to logic zero. No reset has occurred or bit has been cleared (read only). R Valid Reset has occurred. (Cleared when read.) R Port Flag mode inactive Port Flag mode active R Standby Mode (Oscillator active, allows quick power-up) Sleep Mode (Oscillator inactive) R Done Flag bit is cleared (read only). Calibration or Conversion cycle completed (read only). R Normal operation (no calibration) Offset -- Self-Calibration Gain -- Self-Calibration Offset self-cal followed by Gain self-calibration Not Used. Offset -- System Calibration Gain -- System Calibration Not Used.
D23-D22 Latch Outputs, A1-A0 D21-D18 Latch Outputs, D3-D0 D17 D16 Not Used, NU Low Power Mode, LPM
D15-D13 Word Rate, WR2-0 (Note: Rates valid for XIN = 32.768 kHz)
D12 D11-D8 D7
Unipolar/Bipolar, U/B Not Used, NU Reset System, RS
D6 D5 D4 D3 D2-D0
Reset Valid , RV Port Flag, PF Power Save Select, PSS Done Flag, DF Calibration Control Bits, CC2-CC0
* R indicates the bit value after the part is reset
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Performing Conversions
The CS5529 offers two modes of performing conversions: single conversion and continuous conversions. The sections that follow detail the differences and provides examples illustrating how to use the modes. Note that it is assumed that the configuration register has been initialized before conversions are performed.
Single Conversion
A single conversion is performed after the user transmits the single conversion command (0xC0 Hexadecimal). At the completion of the conversion, SDO will fall to logic 0 to indicate that the conversion is complete. To acquire the conversion, the user must issue 8 SCLKs with SDI = logic 0 (i.e. the NULL command) to clear the SDO flag. Upon the falling edge of the 8th SCLK, the SDO pin will present the first bit (MSB) of the conversion word. 24 SCLKs (high, then low) are then required to read the conversion word from the port.
Note: 1) The user must not give an explicit command (other than the NULL command) to read the conversion data register when the PF bit is set to logic 1. 2) The data conversion word must be read before a new command can be entered as the converter will remain in the data mode until the conversion word is read. 3) Once the conversion is read the converter returns to the command mode.
Performing Conversions with PF bit = 0
A single conversion is performed after the user transmits the single conversion command (0xC0 Hexadecimal). At the completion of the conversion, the DF (Done Flag) bit of the configuration register will be set to a logic 1. While the conversion is being performed, the user can read the configuration register to determine if the DF bit is set. Once DF has been set, the read conversion data register command (0x96 Hexadecimal) can be issued to read the conversion data register to obtain the conversion data word.
Note: 1)The DF bit of the configuration register will be cleared to logic 0 when the conversion data register, the gain register, or the offset register is read. Reading only the configuration register will not clear the DF flag bit. 2) If another single conversion command is issued to the converter while it is performing a conversion, the filter will abandon the current conversion and restart a new convolution cycle.
Continuous Conversions
Continuous conversions are performed after the user transmits the continuous conversions command (0xA0 Hexadecimal). At the completion of a conversion, SDO will fall to logic 0 to indicate that the conversion is complete. To read the conversion word, the user must issue 8 SCLKs with SDI = logic 0 (i.e. the NULL command) to clear the SDO flag. Upon the falling edge of the 8th SCLK, the SDO pin will present the first bit (MSB) of the conversion word. 24 SCLKs (high, then low) are then required to read the conversion word from the port. When operating in the continuous conversion mode, the user need not read every conversion. If the user chooses not to read a conversion after SDO falls, SDO will rise one XIN clock cycle before the next conversion word is available and then fall again to signal that another conversion word is available. To exit the continuous conversion mode, the user must issue any valid command, other than the NULL command, to the SDI input when the SDO flag falls. For instance, the user can just read
21
Performing Conversions with PF bit = 1
The PF (Port Flag) bit in the configuration register eliminates the need for the user to monitor the DF (Done Flag) in the configuration register to determine if the conversion is available. When PF is set to a logic 1, SDO's output pin behaves as a flag signal indicating when conversions are completed. SDO will fall to logic 0 once a new conversion is complete.
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the conversion data register again to exit the continuous conversion mode.
Note: 1) If the user begins to clear the SDO flag and read the conversion data, this action must be finished before the conversion cycle which is occurring in the background is complete if the user wants to be able to read the new conversion data. 2) If a CC command is issued to the converter while it is performing a conversion, the filter will stop the current conversion and start a new convolution cycle to perform a new conversion. 3) Continuous conversions aren't allowed unless the port flag bit is set in the configuration register. 4) The converter will remain in data mode and continually perform conversions until the exit command is issued (i.e. to exit the user must read a register).
Output Coding
As shown in the Output Conversion Data Register Descriptions, the CS5529 presents output conversions as a 24-bit conversion word. The first 16 bits of the conversion word represent conversion data. The third byte contains two error flag bits.
D23 MSB D11 3 D22 14 D10 2 D21 13 D9 1 D20 12 D8 LSB D19 11 D7 1 D18 10 D6 1
In the third byte, D7-D4 are always logic 1; D3-D2 are always logic 0; and bits D1-D0 are the two flag bits. The OF (Overrange Flag) bit is set to a logic 1 any time the input signal is: 1) more positive than positive full scale, 2) more negative than zero (unipolar mode), 3) more negative than negative full scale (bipolar mode). It is cleared back to logic 0 whenever a conversion word occurs which is not overranged.The OD (Oscillation Detect) bit is set to a logic 1 any time that an oscillatory condition is detected in the modulator. This does not occur under normal operating conditions, but may occur whenever the input to the converter is extremely overranged. If the OD bit is set, the conversion data bits can be completely erroneous. The OD flag bit will be cleared to logic 0 when the modulator becomes stable. Table 2 and Table 3 illustrate the output coding for the CS5529. Unipolar conversions are output in binary format and bipolar conversions are output two's complement.
D17 9 D5 1 D16 8 D4 1 D15 7 D3 0 D14 6 D2 0 D13 5 D1 OD D12 4 D0 OF
Table 2. Output Conversion Data Register Description (16 bits + flags).
Unipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Offset Binary FFFF FFFF ----FFFE 8000 ----7FFF 0001 ----0000 0000 Bipolar Input Voltage >(VFS-1.5 LSB) VFS-1.5 LSB Two's Complement 7FFF 7FFF ----7FFE 0000 ----FFFF 8001 ----8000 8000
VFS/2-0.5 LSB
-0.5 LSB
+0.5 LSB <(+0.5 LSB)
-VFS+0.5 LSB <(-VFS+0.5 LSB)
Note: VFS in the table equals the voltage between ground and full scale for any of the unipolar gain ranges, or the voltage between full scale for any of the bipolar gain ranges. See text about error flags under overrange conditions. Table 3. CS5529 16-Bit Output Coding.
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Power Supply Arrangements
The CS5529 is designed to operate from single or dual analog supplies and a single digital supply. The following power supply connections are possible: VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V. Figure 10 illustrates the CS5529 connected with a single +5 V supply to measure differential inputs relative to a common mode of 2.5 V. Figure 11 il10 0.1 F 2 VA+ 20
19
+5.0 V Analog Supply
13 VD+ XOUT 10
0.1 F
VREF+
VREF-
32.768 kHz ~ 100 kHz Optional Clock Source
3 5 V Differential Inputs (Gain Register = 1.0) 2.5 V Differential Inputs (Gain Register = 2.0) 1.25 V Differential Inputs (Gain Register = 4.0)
4
AIN+
CS5529
XIN
11
AIND3 D2 D1 D0 A1 A0 VA1
Common Mode = 0 to VA+ + -
18 17 16 7 6 5
8 CS 9 SCLK 15 SDI 14 SDO
Serial Data Interface
DGND 12
Logic Outputs: A0, A1 Switch from VA+ to VAD0-D3 Switch from VD+ to DGND
Figure 10. CS5529 Configured with a +5.0 V Analog Supply.
+2.5 V Analog Supply
0.1 F
2 VA+
20
13 VD+ XOUT 10
+3 V ~ +5 V Digital Supply 0.1 F
VREF+ VREFAIN+ CS5529
32.768 kHz ~ 100 kHz Optional Clock Source
19 3 2.5 V Differential Inputs (Gain Register = 1.0) 1.25 V Differential Inputs (Gain Register = 2.0) 625 mV Differential Inputs (Gain Register = 4.0) 4 18 17 16 7 6 5 -2.5 V Analog Supply Logic Outputs: A0, A1 Switch from VA+ to VAD0-D3 Switch from VD+ to DGND
XIN
11
CS
SCLK
8 9 15 14
AIND3 D2 D1 D0 A1 A0 VA1 0.1 F
SDI SDO
Serial Data Interface
DGND 12
Figure 11. CS5529 Configured with 2.5 V Analog Supplies.
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CS5529
lustrates the CS5529 connected with 2.5 V bipolar analog supplies and a +3 V to +5 V digital supply to measure ground referenced bipolar signals. alog-digital plane split immediately adjacent to the digital portion of the chip See the CDB5529 data sheet for suggested layout details and Applications Note 18 for more detailed layout guidelines. Applications engineering provides a Free and Confidential Schematic Review Service.
PCB Layout
The CS5529 should be placed entirely over an analog ground plane with the DGND pin of the device connected to the analog ground plane. Place the an-
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PIN DESCRIPTIONS
NEGATIVE ANALOG POWER POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT DIFFERENTIAL ANALOG INPUT LOGIC OUTPUT (ANALOG) LOGIC OUTPUT (ANALOG)
LOGIC OUTPUT (DIGITAL)
VAVA+ AIN+
1 2 3 4 5 6
7
20 19 18 17 16 15
14
VREF+ VOLTAGE REFERENCE INPUT
VREFD3
VOLTAGE REFERENCE INPUT LOGIC OUTPUT (DIGITAL) LOGIC OUTPUT (DIGITAL) LOGIC OUTPUT (DIGITAL) SERIAL DATA INPUT
SERIAL DATA OUTPUT
AINA0 A1 D0 CS SCLK XOUT
D2
D1 SDI SDO VD+ DGND XIN
CHIP SELECT SERIAL CLOCK INPUT CRYSTAL OUT
8 9 10
13 12 11
POSITIVE DIGITAL POWER DIGITAL GROUND CRYSTAL IN
Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 10, 11. A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock (powered relative to VD+) can be supplied into the XIN pin to provide the master clock for the device. Control Pins and Serial Data I/O CS - Chip Select, Pin 8. When active low, the port will recognize SCLK. When high the SDO pin will output a high impedance state. CS should be changed when SCLK = 0. SDI - Serial Data Input, Pin 15. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output, Pin 14. SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK - Serial Clock Input, Pin 9. A clock signal on this pin determines the input/output rate of the data for the SDI/SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low.
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CS5529
A0, A1 - Logic Outputs (Analog), Pin 5, 6. The logic states of A0-A1 mimic the states of the D22-D23 bits of the configuration register. Logic Output 0 = VA-, and Logic Output 1 = VA+. D0, D1, D2, D3 - Logic Outputs (Digital), Pin 7, 16, 17, 18. The logic states of D0-D3 mimic the states of the D18-D21 bits of the configuration register. Logic Output 0 = DGND, and Logic Output 1 = VD+. Measurement and Reference Inputs AIN+, AIN- - Differential Analog Input, Pins 3, 4. Differential input pins into the device. VREF+, VREF- - Voltage Reference Input, Pins 20, 19. Fully differential inputs which establish the voltage reference for the on-chip modulator. Power Supply Connections VA+ - Positive Analog Power, Pin 2. Positive analog supply voltage. VA- - Negative Analog Power, Pin 1. Negative analog supply voltage. VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage (+3.0 V or +5 V). DGND - Digital Ground, Pin 12. Digital Ground.
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SPECIFICATION DEFINITIONS
Linearity Error The deviation of a code from a straight line which connects the two end points of the A/D Converter transfer function. One end point is located 1/2 LSB below the first code transition and the other end point is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset The deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 LSB below the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs.
ORDERING GUIDE
Model Number CS5529-AP CS5529-AS Linearity Error (Max) 0.003% 0.003% Temperature Range -40C to +85C -40C to +85C Package 20-pin 0.3" Plastic DIP 20-pin 0.2" Plastic SSOP
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CS5529
PACKAGE DIMENSIONS
20 PIN PLASTIC (PDIP) PACKAGE DRAWING
eB D E1 1 SEATING PLANE e b A2 A A1 b1 L E eC
TOP VIEW
eA
c
BOTTOM VIEW
SIDE VIEW
INCHES DIM A A1 A2 b b1 c D E E1 e eA eB eC L MIN 0.000 0.015 0.115 0.014 0.045 0.008 0.980 0.300 0.240 0.090 0.280 0.300 0.000 0.115 0 MAX 0.210 0.025 0.195 0.022 0.070 0.014 1.060 0.325 0.280 0.110 0.320 0.430 0.060 0.150 15
MILLIMETERS MIN MAX 0.00 5.33 0.38 0.64 2.92 4.95 0.36 0.56 1.14 1.78 0.20 0.36 24.89 26.92 7.62 8.26 6.10 7.11 2.29 2.79 7.11 8.13 7.62 10.92 0.00 1.52 2.92 3.81 0 15
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20L SSOP PACKAGE DRAWING
N
D
E11 A2 A1
L
E
A
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L
MILLIMETERS
NOTE
MIN MAX MIN MAX -0.084 -2.13 0.002 0.010 0.05 0.25 0.064 0.074 1.62 1.88 0.009 0.015 0.22 0.38 2,3 0.272 0.295 6.90 7.50 1 0.291 0.323 7.40 8.20 0.197 0.220 5.00 5.60 1 0.022 0.030 0.55 0.75 0.025 0.041 0.63 1.03 0 8 0 8 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

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